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| (R) (R) ADS-230/ADS-231 Low-Power, 12-Bit, 1.0/1.5MHz Sampling A/D Converter FEATURES * * * * * * * * * * * 12-bit resolution 1.0 and 1.5MHz throughput rates Small 44-pin Leaded Chip Carrier Single +5V supply Low power, 75 and 200mW maximum Low power "standby" mode Outstanding dynamic performance No missing codes over temperature Built-in sample-and-hold Optional two-channel input multiplexer Ideal for both time and frequency-domain applications INPUT/OUTPUT CONNECTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 FUNCTION AGND VBS VB VR/16 VT VTS CH1IN NC CH2IN NC MUX OUT ANALOG INPUT AGND AVS DGND C SEL PD DGND C MD OE RD S/H PIN 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 FUNCTION AVS BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 NC BIT 10 BIT 11 BIT 12 (LSB) EOC INT NC DGND D DGND C DVS TEST CS GENERAL DESCRIPTION The ADS-230 and ADS-231 are 12-bit, high speed CMOS sampling analog-to-digital converters capable of minimum sampling rates of 1.0 and 1.5MHz, respectively. Both models feature excellent dynamic performance including a typical SNR of 72dB for the ADS-230 and 70dB for the ADS-231. The ADS-230 and ADS-231 are packaged in a small 44-pin plastic Leaded Chip Carrier (LCC). Each model contains a fast-settling sample/hold amplifier, a multipass (three-step flash) A/D converter, timing and control logic, three-state outputs, a two-channel multiplexer, and digital error correction circuitry. Digital input and output levels are TTL. Requiring only a single +5V supply, the ADS-230 typically dissipates only 60mW and the ADS-231 only 170mW. Both models offer a low-power "standby" mode resulting in typical power dissipations of 100W and 250W, respectively. The units offer a maximum unipolar input range of 0 to +5V. The exact value of the input range is determined by an externally applied reference voltage. Both models operate over the extended -40 to +85C temperature range. AVS 14,44 DVS 25 VTS 6 VT 5 VR/16 4 VB 3 VBS 2 PIN 43 42 41 40 39 38 37 36 35 33 32 31 29 ANALOG INPUT 12 SAMPLE AND HOLD 12-BIT A/D CONVERTER OUTPUT LATCH AND THREE-STATE BUFFER MUX OUT 11 CH1IN 7 MULTIPLEXER BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 (LSB) INT EOC CH2IN 9 TIMING AND CONTROL CIRCUITRY 30 16 SEL 26,18,15 DGND C 27 DGND D 1,13 AGND 24 TEST 23 CS 22 S/H 21 RD 20 OE 19 MD 17 PD Figure 1. ADS-220/-231 Simplified Block Diagram DATEL, Inc., Mansfield, MA 02048 (U.S.A.) * Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356 * Email: sales@datel.com * Internet: www.datel.com ADS-230/ADS-231 ABSOLUTE MAXIMUM RATINGS PARAMETERS Supply Voltages (VS = AVS = DVS) Input or Output Voltage, any pin Input Current, any pin Total Package Input Current, Power Dissipation, ESD Susceptibilty, Soldering, Infrared, 15 seconds LIMITS -0.3 to +6 -0.3 to VS +0.3 25 50 875 2000 +300 UNITS V V mA mA mW V C (R) (R) PHYSICAL/ENVIRONMENTAL PARAMETERS Operating Temp. Range TA = TJ Thermal Impedance, ja Maximum Junction Temp. TJMAX Storage Temperature Range Package Type MIN. TYP. MAX. UNITS -40 -- +85 C -- 55 -- C/Watt -- -- +150 C -65 -- +150 C 44-pin Plastic Leaded Chip Carrier FUNCTIONAL SPECIFICATIONS (The following specifications apply for TA = TJ = 25C, DVS = AVS = 5.0V, VTS = +4.096V, VBS = AGND, RS = 25ohms and FS = 1.0/1.5MHz for the ADS-230/231 respectively, unless otherwise specified.) ADS-230 -40 to +85C MIN. -0.05 -- -- -- -- -- MAX. AVS+0.05 3 -- 3 -- -- ADS-231 -40 to +85C MIN. -0.05 -- -- -- -- -- MAX. AVS+0.05 3 -- 3 -- -- UNITS V A pF A pF dB +25C ANALOG INPUT Input Voltage Range (Pins 7, 9, 12) Input Leakage Current Input Capacitance MUX On/Off-Channel Leakage MUX Input Capacitance MUX Off-Channel Isolation FIN = 100kHz, -0dB REFERENCE INPUT Reference Input + (Pin 6), VTS Reference Input - (Pin 2), VBS Reference Resistance DIGITAL INPUT Logic Levels Logic "1", VS = 5.5V Logic "0", VS = 4.5V Logic Loading "1" Logic Loading "0" Digital Input Capacitance S/H Pulse Width , tS/H STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Error No Missing Codes Offset Error Gain Error Power Supply Sensitivity, (10%) DYNAMIC PERFORMANCE Total Harmonic Distortion (-0dB) FIN = 100kHz Signal-to-Noise Ratio (wo/distortion, -0dB) FIN = 100kHz Signal-to-Noise Ratio (& distortion, -0dB) FIN = 100kHz Two-Tone Intermodulation Distortion FIN = 102.3, 102.7kHz, (-0dB) Aperature Delay Time, (tAD) A/D Conversion Rate -82 72 71 -80 20 -- 0.4 0.4 -- 0.3 0.2 -- -- -- 0.1 0.1 4 -- -- -- 750 TYP. -- 0.1 25 0.1 7 92 +25C TYP. -- 0.1 25 0.1 7 92 -- 0 500 AVS -- 1000 -- -- 750 -- 0 500 AVS -- 1000 V V Ohms 2 -- -- -- -- 5 -- 0.8 1 1 -- 550 -- -- 0.1 0.1 4 -- 2 -- -- -- -- 5 -- 0.8 1 1 -- 400 V V A A pF ns 12 -- -- 12 -- -- -- 1.5 0.95 -- 2.0 1.5 1.0 0.4 0.4 -- 0.3 0.3 -- 12 -- -- 12 -- -- -- 1.5 0.95 -- 2.0 1.5 0.75 Bits LSB LSB Bits LSB LSB LSB -- 69.5 68 -- -- 1 -70 -- -- -- -- -- -80 70 70 -80 20 -- -- 67.5 67 -- -- 1.5 -70 -- -- -- -- -- dB dB dB dB ns MHz 2 (R) (R) ADS-230/ADS-231 ADS-230 -40 to +85C MIN. 600 60 -- -- -- 35 -- 50 50 20 20 -- MAX. 980 125 20 40 60 10 15 -- -- -- -- -- ADS-231 -40 to +85C MIN. 510 60 -- -- -- 35 -- 50 50 20 20 -- MAX. 660 125 20 40 60 10 15 -- -- -- -- -- UNITS ns ns ns ns ns ns ns ns ns ns ns s +25C TIMING Conversion Time, tCONV Time for Conversion to Start, tEOC Access Time, tACC (CL = 100pF) Three-State Control Time, t1H, t0H RL = 1k, CL = 10pF Delay Time, RD Low to INT High tINTH, CL = 100pF Delay Time, EOC High to INT Low tINTL, CL = 100pF EOC High to Data Valid, tUPDATE MUX Address Setup Time, tMS MUX Address Hold Time, tMH CS Setup Time, tCSS CS Hold Time, tCSH Wake-up Time, tWU PD High to First S/H Low DIGITAL OUTPUT Logic Levels Logic "1" (VS = 4.5V) Logic "0", (VS = 4.5V) Logic Loading "1" Logic Loading "0" Three-State Output Leakage Three-State Output Capacitance Output Coding POWER REQUIREMENTS Power Supply Range +5V Supply, VS = AVS = DVS Power Supply Current DVS Supply Current, DIS AVS Supply Current, AIS Standby Current (AIS +DIS, PD = 0) Power Dissipation -- 2 10 20 -- -- -- -- -- 0.1 5 TYP. 740 95 10 25 35 25 5 -- -- -- -- 1 +25C TYP. 580 90 10 25 35 25 5 -- -- -- -- 1 2.4 -- -- -- -- -- Binary -- 0.4 -360 1.6 3 -- -- -- -- -- 0.1 5 2.4 -- -- -- -- -- Binary -- 0.4 -360 1.6 3 -- V V A mA A pF 4.5 -- -- -- -- 5.5 3 12 -- 75 -- 2 32 50 -- 4.75 -- -- -- -- 5.25 3 37 -- 200 V mA mA A mW Footnotes: When the input voltage at any pin exceeds the power supply rails (below GND or Above VS) the input current must be limited to 25mA or less. The package input current limits to two the number of pins that can meet this constant. In most cases, the maximum derated power dissipation will be reached only during fault conditions. This is the ESD rating for the human body model, with a 100pF capacitor discharged through a 1.5 kilohm resistor. The ESD rating for the machine model is 200V. For best performance, the rising edge of the S/H pulse must not be near either the falling or rising edge of EOC. The recommended values of tS/H are: ADS-230: 5ns 3 ADS-230/ADS-231 PIN DESCRIPTIONS AVS, DVS (R) (R) These are the analog and digital power supply input pins. They should all be connected to the same voltage source. Both AVS pins should be bypassed to AGND and the DVS pin to DGNDD. Bypass using a 0.1F ceramic capacitor in parallel with a 10F tantalum capacitor. These are the analog and digital ground pins. All of the ground pins should be returned to the same potential and connected to a stable, noise-free system ground. AGND is the analog ground. DGNDC is the ground for the digital control lines. DGNDD is the digital ground for the output data bus. These are the three-state data output pins. Output is enabled by RD, CS, and OE. These are the analog input pins to the internal input multiplexer. This is the output of the internal multiplexer, This is the direct input to the sampling A to D converter. This is the multiplexer channel select pin. The input is selected based on the state of SEL when EOC transitions low. A low selects channel one and a high selects channel two. See Table 1. Connect to DGNDC Connect to DVS. This is the Chip Select control input. When low, this pin enables the RD, S/H and OE inputs. This pin can be tied low. This is the Interrupt output pin. When using the Interrupt Interface Mode, this output goes low when a conversion is completed and indicates that the data is available in the output latches. This output is always high when RD is held low. Refer to the Timing Diagrams. This is the End of Conversion output pin. EOC is low during a conversion. This is the Read control input pin. When RD and CS are low, the INT output is reset and, if EOC is high, data appears on the data bus. This pin can be tied low. This is the Output Enable control input pin. The data output pins are in the high impedance state when OE is low. Data appears when OE is high and CS and RD are both low. This pin can be tied high. This is the Sample and Hold control input pin. When CS is low a new conversion is initiated by the falling edge of this input. This is the Power Down control input pin. This pin is held high for normal operation. When the input is low, the A to D converter goes into power standby mode. Bypass this pin to AGND using a 0.1F ceramic capacitor. These are the positive (top) and negative (bottom) voltage reference force input pins, respectively. These are the positive (top) and negative (bottom) voltage reference sense pins, respectively. AGND, DGNDC, DGNDD BIT 1 - BIT 12 CH1IN, CH2IN MUX OUT ANALOG INPUT SEL MD TEST CS INT EOC RD OE S/H PD VR/16 VT, VB VTS, VBS 4 (R) (R) ADS-230/ADS-231 Table 1 shows the coding for MUX channel selection. The output of the MUX is available at the MUX OUT pin. This output allows the user to perform additional signal processing, such as buffering, filtering or gain, before the signal is brought to the ANALOG INPUT pin. If signal processing is not required connect the MUX OUT pin directly to the ANALOG INPUT pin. TECHNICAL NOTES The Analog Input For maximum performance, the source impedance driving the input of the ADS-230/-231 should be as low as possible. A source impedance of less than 100 ohms is recommended. See the Typical Performance Curves. If the signal source has high output impedance, the output should be buffered with an op-amp capable of driving a switched 25pF/100ohm load. Any ringing or instability of the op-amp during the sampling period can cause conversion errors. Using a high-speed buffer also improves the THD performance when using the internal MUX. The MUX onresistance is non-linear over the range of the input voltage; this causes the RC time constant of the equivalent circuit shown in Figure 2 to vary with input voltage. This results in harmonic distortion with increasing frequency. Inserting a buffer between the MUX OUT and ANALOG INPUT terminals will eliminate the loading on RMUX and significantly reduce THD. The analog input of the ADS-230/-231 can be modeled as shown in Figure 2. The S/H switch is closed during the sample period, and open during hold. The hold capacitor (CH) has to be charged to the input voltage by the source within the sample period. The source impedance (RS) will directly effect the charge time. If RS is too large, the voltage across CH will not settle to within 1/2 LSB's of the source voltage before conversion begins. This will result in conversion errors. The combination of RS, RMUX, RSW and CH form a low-pass filter. Therefore, minimizing RS will increase the frequency response of the converter. The settling time to n bits is: tSETTLE = (RS + RMUX + RSW) * CH * n * In(2) The bandwidth of the input circuit is: F (-3dB) = 1/[2 * 3.14 * (RS + RMUX + RSW) * CH] Internal Multiplexer Both the ADS-230 and ADS-231 have an internal multiplexer that is controlled by the logic level on the SEL pin when EOC goes low. See the timing diagrams. The MUX setup and hold times can be determined from the following: tMS(wrt S/H) = tMS -tEOC (min) tMS(wrt S/H) = 50-60 tMS(wrt S/H) = -10ns tMH(wrt S/H) = tMH + tEOC (max) tMH(wrt S/H) = 50 +125 tMH(wrt S/H) = 175ns Note that the -10ns indicates that data on SEL must be valid within 10ns of the S/H pulse going low in order to meet the setup time requirements. SEL must be valid for the length of time determined by the following equation: (tMS + tEOC(max)) - (tMS - tEOC (min)) = 185ns Table 1. Internal Multiplexer Programming SEL 0 1 Channel CH1IN CH2IN ADS-230/231 CH1IN RMUX RS CH2IN MUX OUT VSOURCE TYPICAL VALUES RMUX = 100 RSW = 100 CH = 25pF ANALOG INPUT S/H SWITCH RSW TO COMPARATORS CH Figure 2. ADS-230/-231 Input Stage Model +5V 5% 60 10F VTS NC 4.093V 4.096V VT 0.1F VR/16 0.1F REFERENCE LADDER ADS-230/231 VB 0.003V VBS NC Figure 3. Reference Force Input Only 5 ADS-230/ADS-231 4.096V +5V 1k VT = 4.096V LM4040-4.1 1=5.9mA 7.02V 1~0A 1k VTS RS SENSE LINE 4.096V 0.01F 500 10F VT FORCE LINE 0.1F Rf (R) (R) VR = VT - VB = 4.096V Rf = 0.5 (FORCE LINE IMPEDANCE) RS = 10 (SENSE LINE IMPEDANCE) RLADDER = 750 VR/16 0.1F REFERENCE LADDER ADS-230/231 -2.93V VB = 0.000V 1 = 5.9mA 500 10F 1k -0.003V VB 0.1F Rf FORCE LINE 0.000V RS SENSE LINE 0.000V 0.01F 1~0A VBS Figure 4. Ladder Reference Force and Sense Inputs Reference Inputs Reference voltages are applied to the fully differential VT and VB reference input pins. The resistance of the reference ladder network is typically 750 ohms. Additional parasitic resistances are added by the package leads, wire bonds, conductor traces, etc. These parasitic resistances can introduce voltage drops causing gain and offset errors as large as 6 LSB's at the 12-bit level. These IR drops can be compensated for by sensing the reference voltages at the VTS and VBS reference sense pins and forcing the reference voltage an exact value as shown in Figure 4. Since there is essentially zero current flowing through the sense line there is negligible voltage drop to the inverting input of the op-amp. The voltage at the inverting input of the op-amp, therefore, accurately represents the voltage at the top or bottom of the reference ladder network. The opamp drives the force input and forces the voltages at the ends of the reference ladder network to equal the voltage at the op-amps non-inverting input, plus or minus the opamps input offset voltage. When using this reference configuration with a low offset voltage op-amp, gain and offset errors below 0.5 LSB are readily obtainable. The 0.1 and 10F capacitors on the force inputs provide high frequency decoupling of the reference ladder network. The 500 force resistors isolate the op-amp from the large capacitive load. The 0.01F and 1k network ensures stability at high frequencies. The VR/16 output should be bypassed to analog ground with a 0.1F ceramic capacitor. All bypass capacitors should be located as close to the pins as possible to minimize noise on the reference ladder. If the ADS-230/-231 is used in a frequency domain application then the circuit shown in Figure 3 maybe used. This circuit will introduce several LSB's of gain and offset error, but the dynamic performance will be unaffected. The reference inputs are fully differential and define the fullscale range of the input signal. The maximum range can be up to 5 volts, or when required any span within the 0 to 5V limit may be used. When using lower voltage spans the noise performance will degrade. See the Typical Performance Curves. 6 (R) (R) ADS-230/ADS-231 indicating that the conversion results are latched and may be read by pulling RD low. The falling edge of RD resets the INT line. The High Speed Interface mode is shown in Figure 6. In this mode the output data is always present, and the INT to RD delay is eliminated. The control logic decoding section is shown in Figure 8. Timing The ADS-230/-231 has two modes of operation as shown in Figure 5, 6, 7 and 8. In the Interrupt Interface mode, as shown in Figure 5, the falling edge of S/H holds the input voltage and initiates a conversion when CS is held low. At the end of conversion, the EOC output goes high and the INT output goes low, tAD INPUT N N+1 N+2 CS tTHROUGHPUT tCONV S/H tS/H tAD INPUT N N+1 tTHROUGHPUT tCONV tEOC N+2 EOC tMS tMH SEL N+1 tINT INT tINTH RD tACC BIT 1 - BIT 12 DATA (N-1) DATA (N) t1H.OH N+2 S/H tS/H tEOC EOC tMS tMH SEL N+1 N+2 tUPDATE IT 1 - BIT 12 DATA (N-1) DATA (N) Figure 5. Interrupt Interface Timing (MD = 0, OE = 1) Figure 6. High-speed Interface Timing (MD = 0, OE = 1, CS = 0, RD = 0) tCSS tCSH S/H ADS-230/231 INTERNAL S/H CS CS S/H RD INTERNAL OUTPUT ENABLE RD OE INT OE INT FROM INTERNAL STATE MACHINE Figure 7. CS Setup & Hold Timing for S/H, RD and OE Figure 8. ADS Control Logic 7 ADS-230/ADS-231 Power Supply The ADS-230 and ADS-231 are designed to operate off a single +5V supply. To guarantee proper operation of the converters, only one power supply should be used. If separate analog and digital supplies are used, then the converter must be powered up with the analog supply. The absolute maximum ratings states that all inputs must be between GND -300mV and VS +300mV. When the converter power supply is turned off the maximum input becomes 300mV, which in turn requires that the devices connected to the converter have power removed before power to the converter is removed. There are two analog pins AVS and one digital supply pin DVS. This allows for separate bypassing of the analog and digital sections of the circuit. Both AVS pins should be bypassed to ground with 0.1F ceramic capacitors. At least one of the AVS pins should be bypassed with a 10F tantalum capacitor. The DVS input should be bypassed with a 0.1F ceramic capacitor in parallel with a 10F tantalum capacitor. All bypass capacitor should be located as close to the converter as possible. There are two analog ground pins (AGND), three digital ground pins for the control inputs (DGNDC), and one digital ground pin for the data output lines (DGNDD). Separating the analog section from the digital sections reduces digital (R) (R) interference in the analog circuitry thereby improving the dynamic performance of the converter. When driving a high capacitance digital data bus buffering the output data lines maybe necessary to minimize the DVS and DGND current spikes generated each conversion to charge the data bus capacitance. These large current spikes will couple back to the analog circuitry increasing the converter noise level. Separating the digital outputs from the digital inputs reduces the possibility of ground bounce from the data lines causing jitter on the S/H input. The digital ground planes should be tied together at the digital ground pins. The analog ground plane should be tied to the DGNDD ground plane at the ground return strap for the power supply. S/H Input The clock source driving the S/H input must be free of jitter. For best performance, a crystal oscillator is recommended. For the ADS-230 and ADS-231, a 1.0 and 1.5Mhz square wave will provide a good signal for the respective S/H inputs. In both cases, as long as the duty cycle is near 50%, the S/H pulse widths fall under the maximum allowed. When operating the ADS-230 below 910kHz or the ADS231 below 1.25MHz, the S/H pulse widths must be less than half the respective sample periods. 8 (R) (R) ADS-230/ADS-231 SNR vs. Input Frequency (Through Mux) 80 70 60 50 dB 40 30 20 10 0 dB -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 fIN (kHz) 1000 10 100 fIN (kHz) 1000 THD vs. Input Frequency (Through Mux) SINAD vs. Input Frequency (Through Mux) 80 70 60 50 dB 40 30 20 10 0 10 100 fIN (kHz) 1000 SNR and THD vs. Source Impedance 90 SNR THD 80 80 70 60 SNR and THD vs. Reference Voltage fIN = 100kHz 70 dB dB 60 50 fIN = 100kHz 10 100 1000 10000 50 40 30 20 10 40 0 0 1 2 3 4 REFERENCE VOLTAGE (VT - VB)(V) SNR THD Note: Unless otherwise stated, the following conditions apply: DVS = AVS = 5.0V TA = 25C fS = 1.0MHz fIN = 0dB from full scale SOURCE IMPEDANCE () Conversion Time vs. Temperature 810 800 CONVERSION TIME (ns) 790 780 770 760 5.0V 750 740 4.5V 730 -55 -35 -15 5 25 45 65 85 105 125 -80dB -100dB 5.5V 0dB -20dB -40dB -60dB FFT 100 200 300 400 500 AMBIENT TEMPERATURE (C) FREQUENCY (kHz) SINAD vs. Input Frequency (Analog In) 80 70 60 50 dB dB 40 30 20 10 0 10 100 fIN (kHz) 1000 80 70 60 50 40 30 20 10 0 10 SNR vs. Input Frequency (Analog In) -90 -80 -70 -60 dB -50 -40 -30 -20 -10 0 100 fIN (kHz) 1000 10 THD vs. Input Frequency (Analog In) 100 fIN (kHz) 1000 Typical Performance Curves for ADS-230 9 ADS-230/ADS-231 SINAD vs. Input Frequency (Through Mux) 80 70 60 50 dB dB 40 30 20 10 0 10 100 fIN (kHz) 1000 80 70 60 50 40 30 20 10 0 10 100 fIN (kHz) 1000 dB SNR vs. Input Frequency (Through Mux) -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 fIN (kHz) (R) (R) THD vs. Input Frequency (Through Mux) 1000 SNR and THD vs. Source Impedance 85 80 75 60 70 dB dB 65 60 fIN = 100kH 50 40 30 20 10 0 10 100 1000 10000 0 1 SNR THD 90 80 70 SNR and THD vs. Reference Voltage fIN = 100kH Note: Unless otherwise stated, the following conditions apply: DVS = AVS = 5.0V TA = 25C fS = 1.5MHz fIN = 0dB from full scale CONVERSION TIME (ns) 55 50 SOURCE IMPEDANCE () SNR THD 2 3 4 REFERENCE VOLTAGE (VT - VB)(V) Conversion Time vs. Temperature 630 0dB 620 -20dB 610 -40dB 600 5.5V 590 580 4.5V 570 -55 -35 -15 5 -100dB 25 45 65 85 105 125 100 5.0V -80dB -60dB FFT 200 300 400 500 AMBIENT TEMPERATURE (C) FREQUENCY (kHz) SINAD vs. Input Frequency (Analog In) 80 70 60 50 dB dB 40 30 20 10 0 10 100 fIN (kHz) 1000 80 70 60 50 40 30 20 10 0 10 SNR vs. Input Frequency (Analog In) -90 -80 -70 -60 dB -50 -40 -30 -20 -10 0 100 fIN (kHz) 1000 10 THD vs. Input Frequency (Analog In) 100 fIN (kHz) 1000 Typical Performance Curves for ADS-231 10 (R) (R) ADS-230/ADS-231 Linearity Error vs. Reference Voltage 0.6 0.5 0.4 0.3 0.2 0.1 0.0 380 340 LINEARITY ERROR (LSB) 300 260 220 5.0V 180 5.5V 140 100 1 2 3 4 5 60 0.0 1.0 2.0 3.0 4.0 5.0 4.5V Mux ON Resistance vs. Analog Input vs. VS Offset and Fullscale Error vs. Reference Voltage 1.50 OFFSET AND FULLSCALE ERROR (LSB) 1.25 1.00 0.75 0.50 0.25 0.00 1 OFFSET 2 3 4 5 FULLSCALE REFERENCE VOLTAGE (VT -VB)(V) LINEARITY ERROR (LSB) REFERENCE VOLTAGE (VT -VB)(V) ANALOG INPUT (V) Digital Supply Current vs. Temperature vs. DVS 2.3 ANALOG SUPPLY CURRENT (mA) DIGITAL SUPPLY CURRENT (mA) 34 33 32 31 30 29 Analog Supply Current vs. Temperature vs. AVS DIGITAL SUPPLY CURRENT (A) 5.25V 5.0V 4.75V 260 240 220 200 180 160 140 120 100 80 60 40 20 0 Current Consumption in Standby Mode vs. Voltage on Digital Input Pins 2.2 5.25V 5.0V 2.1 4.75V 2.0 1.9 -55 -35 -15 5 25 45 65 85 105 125 28 -55 -35 -15 5 25 45 65 85 105 125 0 1 2 3 4 5 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) INPUT VOLTAGE (V) EOC Delay Time (tEOC) vs. Temperature vs. VS 110 Note: Unless otherwise stated, the following conditions apply: DVS = AVS = 5.0V TA = 25C EOC DELAY TIME (tEOC) (ns) 105 100 4.75V 95 5.0V 5.25V 90 85 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (C) Typical Performance Curves, ADS-230/-231 11 ADS-230/ADS-231 MECHANICAL DIMENSIONS INCHES (mm) 0.650 - 0.656 (16.51 - 16.66) PIN 1 INDENT 1 44 (R) (R) 45 x 0.045 (1.14) 40 39 6 7 ADS-230/231 17 18 0.500 (12.70) TYP 0.165 - 0.180 (4.19 - 4.57) TYP 0.090 - 0.130 (2.29 - 3.30) TYP 28 29 0.050 (1.27) TYP 0.685 - 0.695 (17.40 - 17.65) TYP 0.026 - 0.032 (0.66 - 0.81) TYP 45 x 0.045 (1.14) 0.020 (0.51) MIN TYP 0.013 - 0.021 (0.33 - 0.53) TYP 0.590 - 0.630 (14.99 - 16.00) TYP ORDERING INFORMATION Model ADS-230 ADS-231 Throughput Rate 1.0MHz 1.5MHz Operating Temperature Range -40C to +85C -40C to +85C ISO 9001 R E G I S T E R E D DS-0301 03/97 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: sales@datel.com Data sheet fax back: (508) 261-2857 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark. |
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